Intel Semiconductor Process Engineer Interview Questions

Introduction

Semiconductor Process Engineers are the architects of the physical world that makes modern computing possible. Every transistor, every interconnect wire, and every dielectric layer on a silicon wafer is the result of a precisely controlled sequence of process steps — lithography, deposition, etch, implantation, chemical mechanical planarisation, and metrology — each of which must be engineered to angstrom-level precision across hundreds of wafers simultaneously. At advanced process nodes (Intel 3, TSMC N3, Samsung 3GAE), the margin for error is measured in atoms: a gate dielectric that is 3 angstroms too thick degrades drive current; a fin profile that deviates 2nm from specification shifts threshold voltage across the die; a CMP process that removes 5nm too much of interlayer dielectric creates a resistive via that fails at operating temperature. Process engineers own the development, qualification, and yield maintenance of these steps in production.

The role spans the full spectrum from front-end-of-line (FEOL) — where transistor structures including fins, gates, source/drain regions, and contacts are formed — through back-end-of-line (BEOL) — where the 10–15 metal interconnect layers that wire the transistors together are deposited, patterned, and planarised. At advanced nodes, process engineers work on technologies including FinFET and Gate-All-Around (GAA) nanosheet transistors, extreme ultraviolet (EUV) lithography with sub-10nm resolution, atomic layer deposition (ALD) for conformal sub-nanometre films, and low-k dielectric integration that must survive thermal budgets, mechanical stress, and chemical attack throughout the full process flow. Beyond process development, semiconductor process engineers are responsible for statistical process control (SPC), design of experiments (DOE), yield loss analysis, and the cross-functional collaboration with device, integration, and equipment engineers that turns a process recipe into a reliable manufacturing flow.

Interviews for Semiconductor Process Engineer roles are designed to probe deep technical understanding of process physics — not just familiarity with process names. Candidates are expected to reason from first principles about thin film deposition kinetics, etch selectivity mechanisms, diffusion and implant profiles, and the physical and chemical origins of defects and yield loss. The five questions below span the critical process domains: lithography and patterning, thin film deposition, etch and integration, CMP, and yield engineering. Each is grounded in the real challenges of advanced node process development and manufacturing.

Interview Questions

Question 1: EUV Lithography Process Window and Stochastic Defectivity

Interview Question

Your team is qualifying an EUV lithography process for the metal-2 (M2) layer at a 28nm pitch (14nm half-pitch) on an Intel 3 / TSMC N3-equivalent process node. The design calls for lines and spaces of equal width (14nm lines / 14nm spaces). After exposing and developing 50 wafers, your CD-SEM and e-beam inspection data shows three yield-limiting defect types: (1) line edge roughness (LER) of 3.2nm 3σ on the resist pattern — exceeding the 2.0nm spec; (2) stochastic bridge defects (unintended resist bridges between adjacent lines) occurring at a rate of 0.08 bridges per µm² — above the 0.02/µm² yield-loss threshold; (3) after pattern transfer via etch, you observe a CD bias of +2.1nm (lines are wider than drawn after etch, reducing the space CD from 14nm to 11.9nm) that varies ±0.8nm across the wafer.

For each defect type, explain the physical mechanism, identify the process levers you would adjust, and describe how you would set up a DOE to close the gaps to specification.

Why Interviewers Ask This Question

EUV lithography process window engineering is among the most technically demanding challenges in semiconductor manufacturing, and the three defect types described represent the dominant yield limiters in EUV patterning at sub-20nm pitches. LER, stochastic bridging, and CD bias after etch are not independent problems — they are coupled through dose, focus, resist chemistry, and etch process interactions. This question tests whether a candidate understands process physics at the level required to diagnose and correct real yield problems, not just identify the symptoms.

Example Strong Answer

Defect 1: Line Edge Roughness (LER) 3.2nm 3σ — exceeds 2.0nm spec

Physical mechanism:

LER in EUV resist is fundamentally driven by photon shot noise and resist polymer inhomogeneity. At EUV wavelengths (13.5nm), the photon energy is 91eV — much higher than DUV (248nm/193nm). However, the number of photons per unit area at practical doses is much lower than DUV because EUV sources have limited power. At a typical EUV dose of 30 mJ/cm² and 28nm pitch geometry, the number of photons arriving per resolution element is approximately:

Photons/element = (Dose × Area) / (Photon energy)
                = (30×10⁻³ J/cm² × (14×10⁻⁷ cm)²) / (91 × 1.6×10⁻¹⁹ J)
                ≈ 40 photons per 14nm × 14nm pixel

With only ~40 photons per pixel, the shot noise (Poisson statistics: σ = √40 ≈ 6.3 photons, or ~16% relative noise) creates random spatial dose fluctuations that manifest as rough resist edges. Additionally, the resist polymer has a finite molecular weight — each polymer molecule is ~3–5nm in size, and the dissolution threshold is set at the molecular level. At 14nm spaces, only ~3–4 polymer molecules span the space width, making dissolution behaviour statistically noisy.

Process levers:

• Increase EUV dose: Higher dose increases photon count per pixel, reducing relative shot noise (σ/N decreases as √N increases). Increasing dose from 30 to 50 mJ/cm² reduces relative photon noise from 16% to 12%. Trade-off: higher dose increases EUV scanner throughput cost (fewer wafers per hour) and can cause resist footing or reduced contrast at over-exposure.

• Reduce resist molecular weight / polymer size: Switch to a smaller-molecular-weight resist formulation (e.g., metal-oxide resist, such as tin-oxo clusters used by JSR/Inpria). Metal-oxide resists have 2–3nm resolution elements vs 5nm polymer chains — directly reducing the molecular-level LER contribution.

• Post-develop bake (PDB) optimization: A controlled thermal anneal of the developed resist pattern (80–110°C, 30–60 seconds) causes partial resist reflow that smooths edge roughness. The trade-off is CD bias from the reflow — optimise temperature to smooth LER without shifting CD.

• Process window centering — dose-focus matrix DOE: Run a dose-focus matrix exposing 5×5 arrays of dose (25–45 mJ/cm², 5 mJ/cm² steps) × focus offset (−60nm to +60nm, 30nm steps). Measure LER at each point. LER has a dose-focus optimum that may differ from the CD-optimum point — identify the process window that satisfies both LER ≤ 2.0nm and CD within ±2nm tolerance.

Defect 2: Stochastic bridge defects 0.08/µm² — exceeds 0.02/µm² threshold

Physical mechanism:

Stochastic bridges occur when an isolated clump of resist polymer in a nominally clear space region fails to dissolve during development — either because: (a) the local dose in that pixel was below the dissolution threshold due to shot noise, or (b) a resist particle or acid diffusion non-uniformity created a locally under-exposed island. At 14nm spaces, a single undissolved polymer chain of 4nm diameter is enough to create a "bridge" that, after etch, becomes a metal short between adjacent lines — an immediate yield killer.

Process levers:

• Increase dose-to-clear margin: The dose margin between the dissolution threshold and the operating dose (dose-to-clear ratio) directly controls bridge probability. If the operating dose is only 5% above the dissolution threshold, shot noise fluctuations regularly push pixels below the threshold. Increase the dose margin to 20–30% above dissolution threshold.

• Developer concentration and development time: Use a higher-concentration developer (TMAH 2.38% vs 1.19%) or extend development time. More aggressive development clears marginally exposed resist but risks CD loss at edges. Puddle development with multiple dispense cycles improves development uniformity.

• Resist underlayer (anti-reflection coating) optimisation: A non-uniform BARC (Bottom Anti-Reflection Coating) can create local dose perturbations. Verify BARC thickness uniformity across the wafer to < 1nm 3σ using spectral ellipsometry.

• Stochastic bridge DOE: Design a multi-factor DOE varying: dose (primary factor), BARC thickness (±2nm around nominal), developer concentration (1.19% vs 2.38%), and development time (30s vs 60s). Measure bridge density via e-beam inspection on 10 fields per wafer (sampling ~10,000 µm² per wafer). Target: identify conditions where bridge rate < 0.02/µm² while maintaining LER < 2.0nm — the two constraints are coupled and must be optimised simultaneously.

Defect 3: +2.1nm etch CD bias with ±0.8nm wafer non-uniformity

Physical mechanism:

The +2.1nm CD bias (lines wider after etch than drawn in resist) combined with ±0.8nm non-uniformity is a loading effect in the reactive ion etch (RIE) process. In a fluorine-based or chlorine-based plasma etch of the hardmask or metal layer beneath the resist:

• Microloading: Pattern density varies across the wafer. High-density areas (where many lines are close together) consume etchant species faster, locally depleting the plasma chemistry. Lower local etchant concentration = slower etch rate = less lateral undercut of the line = wider final CD (less etch bias). Low-density areas have excess etchant, faster etch rate, and more undercut.

• The +2.1nm bias itself: The resist passivation layer formed during the etch (polymer deposition on sidewalls from fluorocarbon precursors) is protecting the resist line sidewalls more than intended. The passivation film is thicker than optimal, reducing lateral etch rate and leaving the line wider than drawn.

Process levers:

• Reduce fluorocarbon precursor flow (e.g., C₄F₈ or CHF₃): Less fluorocarbon in the plasma reduces sidewall passivation film thickness, increasing lateral etch rate and reducing the positive CD bias. Decrease C₄F₈ flow by 10–20% and measure CD change.

• Increase Ar dilution: Argon dilution in the etch plasma reduces the partial pressure of reactive species — reducing both the etch rate and the passivation rate, but typically more selectively reducing passivation.

• Wafer-level compensation for non-uniformity: The ±0.8nm across-wafer non-uniformity suggests a non-uniform plasma density. Tune the etch chamber's edge ring voltage or the magnetic confinement coils to improve plasma uniformity across the wafer diameter.

• CD bias closure DOE: Design a 3-factor DOE varying: C₄F₈ flow (±20% around nominal), RF power (±15%), and chamber pressure (±10%). Measure CD bias and CD non-uniformity at 49-point across-wafer sites for each run. Use response surface methodology (RSM) to find the operating point that minimises |CD bias| and CD range simultaneously.

Key Concepts Tested

• EUV photon shot noise: Poisson statistics applied to photon count per resolution element

• Resist LER mechanisms: shot noise vs polymer chain granularity

• Metal-oxide resists as a smaller-molecular-weight alternative to polymer resists

• Stochastic defect probability: dose-to-clear margin and development chemistry

• RIE loading effects: microloading, fluorocarbon sidewall passivation, and CD bias

• DOE methodology: dose-focus matrix, multi-factor RSM, coupled constraint optimisation

Follow-Up Questions

1. "Your dose-focus matrix DOE identifies a process window where LER ≤ 2.0nm and bridge rate < 0.02/µm² simultaneously. However, this optimum point is at the edge of the scanner's focus stability specification — the process window depth-of-focus (DOF) is only ±15nm, but the scanner's focus control has ±20nm wafer-to-wafer repeatability. How do you modify the patterning approach to improve the effective DOF without changing the resist formulation?"

1. "After fixing the etch CD bias to within ±0.5nm, your electrical yield data shows that metal-2 resistance per unit length is 8% higher than simulation predicts. The CD is correct, the metal thickness is correct as measured by XRF, and the TEM cross-section shows no visible voids. What process-level mechanisms could cause elevated resistance in a metal line with correct dimensional metrology, and which characterisation techniques would you use to identify the root cause?"

Question 2: Atomic Layer Deposition — Conformality, Nucleation, and Process Integration

Interview Question

You are developing an ALD (Atomic Layer Deposition) process for a hafnium oxide (HfO₂) high-k gate dielectric on a FinFET gate stack. The fin structure has an aspect ratio of 8:1 (fin height 52nm, fin width 6.5nm). The target HfO₂ thickness is 1.8nm equivalent oxide thickness (EOT). Your ALD process uses HfCl₄ precursor and H₂O oxidant at 300°C. Initial characterisation shows three problems: (1) TEM cross-sections show the HfO₂ is 2.2nm thick on the fin top and sidewalls but only 1.4nm in the fin bottom corner — a 36% thickness non-conformality; (2) C-V measurements on finished FETs show a higher-than-expected interface trap density (Dit) of 4×10¹² cm⁻²eV⁻¹ at the Si/HfO₂ interface; (3) after the post-deposition anneal (PDA) at 600°C, XRD shows the HfO₂ has partially crystallised with a mixed monoclinic/orthorhombic phase, causing ΔVth shifts of 80mV across the wafer.

For each problem, explain the physical and chemical mechanism, and propose the process change that addresses it.

Why Interviewers Ask This Question

ALD of high-k dielectrics is one of the most technically demanding processes in advanced CMOS fabrication, and HfO₂ gate dielectric quality directly determines transistor performance and reliability. The three problems described represent the three dominant integration challenges: ALD conformality (a transport and surface reaction kinetics problem), interface trap passivation (a surface chemistry problem), and dielectric crystallisation (a thermodynamics and process integration problem). This question tests deep understanding of thin film physics and chemistry, not just familiarity with ALD as a process name.

Example Strong Answer

Problem 1: 36% thickness non-conformality in the fin bottom corner

Physical mechanism — reaction-limited vs transport-limited ALD:

ALD conformality depends on whether the process operates in the reaction-limited regime (where the precursor supply to all surfaces is sufficient for full saturation within each half-cycle) or the transport-limited regime (where precursor molecules are depleted before reaching deep into high-aspect-ratio features).

The Knudsen number (Kn = mean free path / feature dimension) determines the transport regime:

• At 300°C, 1 Torr, the mean free path of HfCl₄ is approximately 50–100 µm

• Feature dimension (fin bottom corner): ~1–2nm effective aperture

• Kn >> 1: molecular flow regime — molecules travel in straight lines without inter-molecular collisions, meaning they can penetrate deep features only if the sticking coefficient is low enough for molecules to "see" the bottom

The non-conformality indicates that the HfCl₄ sticking coefficient is too high — precursor molecules adsorb on the upper fin surfaces before reaching the bottom corner, depleting the precursor before full saturation at the bottom.

Process fix:

• Reduce precursor partial pressure or increase exposure time: Lower the HfCl₄ partial pressure (dilute with N₂ carrier gas) to reduce the probability of adsorption per surface encounter, allowing more molecules to penetrate to the fin bottom. Alternatively, extend the HfCl₄ exposure time (pulse duration) from e.g., 0.1s to 0.5s — giving more time for molecules to diffuse to the fin corners before saturation.

• Increase substrate temperature: A higher deposition temperature (330°C vs 300°C) reduces the sticking coefficient by increasing the surface desorption rate, improving the balance between adsorption and desorption that governs conformality. Verify that the higher temperature remains within the ALD saturation regime (not CVD regime).

• Reduce chamber pressure during exposure: Lower pressure increases mean free path, improving the penetration of precursor into high-aspect-ratio features. Use a pressure-modulated ALD (PM-ALD) approach: high pressure during the H₂O oxidant step (to ensure full oxidation), low pressure during the HfCl₄ step (to improve conformality).

Problem 2: Interface trap density Dit = 4×10¹² cm⁻²eV⁻¹ — too high

Physical mechanism — Si/HfO₂ interface defects:

Interface traps at the Si/HfO₂ boundary arise from two sources: (a) dangling Si bonds — Si surface atoms that are not fully bonded to either the substrate or the dielectric, leaving unsatisfied valence electrons that act as charge traps; and (b) interfacial reaction products — Si suboxide species (SiOx, x < 2) or Si-Hf silicates formed at the interface that create mid-gap trap states.

The HfCl₄/H₂O chemistry at 300°C deposits HfO₂ directly on the HfSiON interface passivation layer or the bare silicon surface. The Cl byproduct from the HfCl₄ half-reaction (HCl released during the ligand exchange) can react with Si surface atoms, creating Si-Cl bonds that are not fully passivated.

Process fix:

• Chemical oxide interfacial layer: Before ALD, grow a controlled thin chemical oxide (SiO₂, 0.5–0.8nm) using ozonated DI water or dilute HNO₃. This chemical oxide passivates Si dangling bonds and provides a well-controlled, uniform surface for HfO₂ nucleation. The trade-off: the SiO₂ interlayer increases EOT, requiring compensation by reducing the HfO₂ physical thickness.

• Post-ALD forming gas anneal (FGA): Anneal in H₂/N₂ forming gas (5% H₂ in N₂, 400–450°C, 30 minutes) after gate stack deposition. Atomic hydrogen generated at the gate metal surface diffuses to the Si/dielectric interface and passivates dangling Si bonds as Si-H bonds. This is the standard Dit reduction step and can reduce Dit from 4×10¹² to < 5×10¹¹ cm⁻²eV⁻¹.

• Replace H₂O oxidant with ozone (O₃): O₃ is a stronger oxidant than H₂O and provides more complete oxidation of Hf precursor residues at the interface. O₃-based ALD reduces interface Cl contamination by more aggressively removing HCl byproducts from the growing film.

Problem 3: HfO₂ crystallisation (monoclinic/orthorhombic) causing Vth shifts

Physical mechanism — HfO₂ phase diagram and grain boundary Vth shift:

HfO₂ has three primary crystal phases below 1,000°C: monoclinic (stable below 1,700°C), tetragonal (stable 1,700–2,300°C), and orthorhombic (high-pressure phase). Amorphous HfO₂ is the desired phase for gate dielectrics — it has a uniform dielectric constant (k ≈ 16–20) without grain boundaries.

Crystallisation during the 600°C PDA occurs because:

• Amorphous HfO₂ has a crystallisation onset temperature of ~450–500°C — well below the 600°C anneal

• Mixed monoclinic/orthorhombic phases have different k values: monoclinic k ≈ 16, orthorhombic k ≈ 40–70 (the latter exploited in ferroelectric memory). The k spatial variation from grain-to-grain creates local EOT variations that manifest as Vth shifts.

• Grain boundaries between crystalline HfO₂ grains are regions of elevated oxide fixed charge — causing additional Vth shifts that vary depending on where the grain boundary falls relative to the transistor channel.

Process fix:

• Dope HfO₂ with Si or Al to suppress crystallisation: Incorporate 5–20% SiO₂ (by using TEOS/H₂O ALD cycles alternated with HfCl₄/H₂O cycles) or Al₂O₃ to form HfSiO or HfAlO dielectrics. Si and Al act as crystallisation inhibitors — they pin the amorphous phase by disrupting the Hf-O network regularity, raising the effective crystallisation temperature from 450°C to > 800°C. Most production gate dielectrics use HfSiO or HfAlO for this reason.

• Reduce PDA temperature: A 600°C PDA is unusually high for a gate dielectric anneal — reduce to 400–450°C. The PDA purpose is typically to relieve ALD-induced film stress and improve Si-O bond passivation, both of which are achievable at lower temperatures. Verify with C-V measurements that the lower-temperature PDA still achieves the target Dit.

• Nitrogen incorporation (HfSiON): Incorporate nitrogen into the gate dielectric by exposing to NH₃ or N₂ plasma during the PDA. Nitrogen in HfO₂ simultaneously: suppresses crystallisation (N disrupts crystallographic ordering), reduces boron diffusion from the poly-Si or metal gate (important for gate electrode integration), and slightly increases k value. Most production hafnium-based high-k dielectrics are HfSiON.

Key Concepts Tested

• ALD conformality physics: Knudsen transport, sticking coefficient, saturation vs transport-limited regime

• Si/high-k interface trap density: dangling bond mechanisms, HCl contamination, forming gas anneal passivation

• HfO₂ phase diagram: amorphous vs monoclinic vs orthorhombic and temperature-driven crystallisation

• Crystallisation suppression: Si/Al doping of HfO₂ to form HfSiO or HfAlO alloys

• Ozone vs H₂O oxidant trade-offs in ALD chemistry

• EOT vs physical thickness trade-off for SiO₂ interfacial layers

Follow-Up Questions

1. "You switch to HfSiO (20% SiO₂) to suppress crystallisation and the XRD shows the film remains amorphous after a 600°C PDA. However, the EOT measured by C-V has increased from the target 1.8nm to 2.4nm, degrading the drive current by 11%. Calculate the physical thickness of HfSiO required to achieve 1.8nm EOT given that the dielectric constant of HfSiO is k = 14 (vs SiO₂ k = 3.9), and explain what process change would reduce the EOT back to target without sacrificing amorphous-phase stability."

1. "After optimising all three problems individually, you run a split lot combining all three fixes: lower pressure HfCl₄ exposure for conformality, chemical oxide interfacial layer for Dit, and HfSiO for crystallisation suppression. The combined result shows excellent Dit and phase stability, but the conformality in the fin bottom corner has degraded again — now showing 1.0nm vs 2.2nm on the top. Explain the mechanism by which the chemical oxide interfacial layer or the HfSiO composition change could worsen conformality, and how you would re-optimise the combined process."

Question 3: CMP Process Engineering — Dishing, Erosion, and Pattern Density Effects

Interview Question

You are the CMP (Chemical Mechanical Planarisation) process engineer responsible for the tungsten (W) contact plug CMP step in the FEOL of a 5nm-node process. After W deposition fills the contact holes, the CMP step must remove the overburden tungsten and stop on the silicon dioxide (SiO₂) ILD (interlayer dielectric). Post-CMP metrology shows three yield-limiting problems: (1) tungsten dishing: in isolated large contact arrays (10µm × 10µm metal fill areas), the W surface is recessed 18nm below the SiO₂ surface — exceeding the 8nm dishing spec; (2) oxide erosion: in dense contact areas (contact pitch 50nm, 70% fill density), the SiO₂ ILD surface is 22nm lower than in open areas — exceeding the 10nm erosion spec; (3) contact resistance (Rc) variation: the 90th percentile Rc is 3.2× higher than median Rc, correlated with the dishing and erosion areas.

Diagnose the mechanism behind each problem and describe the CMP process changes and upstream process changes that would close all three to specification.

Why Interviewers Ask This Question

CMP is a critical gating process step in semiconductor manufacturing — it establishes the planar surface topology that all subsequent lithography levels depend on, and CMP non-uniformity directly causes yield loss through contact resistance variation, metal line resistance, and inter-layer short circuits. The three problems described — dishing, erosion, and pattern-density-driven variation — are the three canonical CMP failure modes that process engineers encounter at every node. This question tests whether a candidate understands CMP physics (Preston's equation, selectivity, pattern density effects) deeply enough to diagnose and fix real yield problems.

Example Strong Answer

CMP physics background:

The Preston equation describes the material removal rate (MRR) in CMP:

MRR = Kp × P × v

Where:
  Kp = Preston coefficient (material/slurry-specific)
  P  = applied pressure
  v  = relative velocity between wafer and pad

Both P and v depend on the local pattern geometry: in recessed areas (inside a W contact), the pad deflects into the recess and the local pressure is reduced. In raised areas (W overburden on ILD), the local pressure is elevated. This pressure non-uniformity drives the dishing and erosion mechanisms.

Problem 1: W dishing 18nm (spec: 8nm) in large contact arrays

Mechanism:

In large fill areas (10µm × 10µm W pad), the CMP pad is compliant enough to conform to the W surface as it recesses below the surrounding SiO₂ level. The pad contacts the W surface directly and continues polishing it even after the W is nominally planar with the SiO₂ — because the pad's elastic modulus allows it to apply pressure into the recess. The softer the pad, the more it conforms and the greater the dishing.

Additionally, the W slurry has finite selectivity between W and SiO₂: if the slurry removes W at 200nm/min and SiO₂ at 20nm/min (W:SiO₂ selectivity = 10:1), the W is removed 10× faster even when exposed simultaneously with SiO₂ — driving W below the SiO₂ level.

CMP process fixes:

• Use a harder CMP pad: A harder pad (higher Shore D durometer, e.g., IC1400 Stacked vs IC1000) has less compliance and cannot conform into the W recess as deeply. This directly reduces dishing by limiting pad deflection. Trade-off: harder pads can increase oxide erosion in dense areas (less conformality = more uniform pressure, which is good for erosion).

• Reduce polishing time at the endpoint / change endpoint detection: Use optical endpoint detection (OED) or eddy current monitoring to detect the W-to-SiO₂ transition precisely. Terminate the W polish within 3–5 seconds of endpoint rather than using a timed overpolish. Each additional second of overpolish removes additional W from large fill areas.

• Slurry chemistry optimisation — increase W:SiO₂ selectivity: Use a slurry with higher selectivity (W:SiO₂ > 50:1) so that after W endpoint, further slurry contact removes negligible SiO₂ and W relative to each other. High-selectivity slurries typically use inhibitor additives (BTA — benzotriazole) that passivate the W surface after removal.

Problem 2: Oxide erosion 22nm (spec: 10nm) in dense contact areas

Mechanism:

In dense contact areas (70% fill density, 50nm pitch), the many closely spaced contact holes leave only thin walls of SiO₂ between them. During W CMP, the slurry loads with W debris particles in the dense area, and the pad-to-wafer pressure is distributed across both the W plugs and the thin SiO₂ walls. The thin SiO₂ walls experience high local mechanical stress from the pad and also contact the abrasive slurry directly. Two mechanisms combine:

1. Mechanical erosion: The narrow SiO₂ columns between contacts experience higher stress per unit area (stress concentration at thin features), and the silica abrasives in the slurry physically abrade the SiO₂ surface.

1. Chemical over-polish: Once the W overburden clears in the dense area (which happens earlier than in sparse areas, because the effective W removal area is smaller), continued polishing removes SiO₂ at the base of the contacts — the SiO₂ is now directly exposed to the slurry while isolated areas still have W overburden protecting their surrounding SiO₂.

CMP process fixes:

• Reduce slurry abrasive size and concentration: Smaller abrasive particles (70nm → 30nm colloidal silica) and lower abrasive concentration (3 wt% → 1 wt%) reduce the mechanical erosion rate of SiO₂ in dense areas without proportionally reducing W removal rate (which has a larger chemical component).

• Two-step CMP sequence: Step 1 uses a high-selectivity slurry (W:SiO₂ > 50:1) for bulk W removal — fast W removal, stops on SiO₂. Step 2 switches to a lower-selectivity buffing slurry for final planarisation — slow removal of both W and SiO₂ uniformly, controlled over-polish for planarisation. The two-step approach decouples bulk removal efficiency from over-polish uniformity.

• Pattern density compensation (upstream design or CMP dummy fill): Add metal CMP dummy fill tiles in sparse areas to equalise the effective metal density across the die. Uniform metal density (targeting 50–60% across all 50µm × 50µm regions) reduces the density-dependent pressure variation that drives both dishing and erosion. This is implemented as a design rule by the EDA tool team for the metal layer.

Problem 3: 90th percentile Rc 3.2× higher than median — correlated with dishing/erosion

Mechanism:

Elevated contact resistance is directly caused by:

1. W dishing: A dished W plug has a W surface recessed 18nm below the SiO₂ level. The subsequent metal-1 line must bridge down into the recess to contact the W plug. If the M1 deposition doesn't fully fill the recess (especially for conformal PVD or CVD processes with limited conformality), the effective contact area between M1 and the W plug is reduced — increasing Rc proportionally to the contact area reduction.

1. Oxide erosion + plug height variation: In eroded areas, the W plug height above the wafer substrate is also reduced (the plug was planarised into an already-eroded ILD surface). A shorter W plug has higher series resistance contributing to Rc.

1. W surface oxidation in dished contacts: A recessed W surface is partially shielded from the post-CMP cleaning chemistry — oxidised W (WO₃) formed during CMP exposure to H₂O₂-containing slurry may not be fully removed in dished contacts. WO₃ has ~1,000× higher resistivity than W metal, and even 1–2nm of surface oxide directly degrades Rc.

Fixes:

• Post-CMP clean optimisation: Use a reducing clean chemistry (dilute HF + reducing agent) specifically designed to remove WO₃ from W plug surfaces. Validate clean effectiveness with XPS measurement of W:WO₃ surface ratio before and after clean.

• W plug overfill with controlled etch-back: Instead of relying on CMP to achieve the exact plug height, deposit W with a controlled overfill (W stands proud of the SiO₂ by 5–10nm before CMP). After CMP, a short isotropic W etch-back (using SF₆-based RIE) precisely controls the final W plug height relative to the SiO₂ — decoupling plug height from CMP uniformity.

Key Concepts Tested

• Preston equation: pressure × velocity dependence of CMP removal rate

• Pad compliance and its role in W dishing in large fill areas

• Pattern density effects: loading and selectivity-driven erosion in dense contact regions

• W:SiO₂ selectivity: chemical vs mechanical removal rate components

• Two-step CMP: bulk removal step decoupled from planarisation step

• WO₃ surface oxidation and its contribution to elevated contact resistance

• CMP dummy fill for pattern density equalisation

Follow-Up Questions

1. "After implementing the two-step CMP and dummy fill changes, dishing is reduced to 6nm (within spec) and erosion is reduced to 9nm (within spec). However, wafer-level Rc uniformity still shows a systematic centre-to-edge gradient: contacts at the wafer edge have Rc 40% higher than contacts at the wafer centre, even in areas with identical pattern density. The centre-to-edge Rc gradient is correlated with a 3nm centre-to-edge W plug height gradient measured by cross-section TEM. What CMP process parameter most likely drives this centre-to-edge planarisation non-uniformity, and what hardware adjustment on the CMP tool would correct it?"

1. "The next process node requires reducing the contact pitch from 50nm to 32nm while maintaining the same W CMP step. At 32nm pitch with 70% fill density, the SiO₂ walls between contacts are only 9.6nm wide. Explain why the erosion problem will be significantly worse at 32nm pitch for the same CMP process conditions, and what fundamental process change (beyond optimising the existing CMP chemistry) would be required to manage CMP-induced erosion at this geometry."

Question 4: Ion Implantation — Channelling, Damage Recovery, and Shallow Junction Formation

Interview Question

You are developing the source/drain extension (SDE) implant for a p-type FinFET on a <100> silicon substrate at a 5nm node. The SDE must achieve: junction depth (Xj) of 8nm, peak dopant concentration of 2×10²⁰ cm⁻³, and sheet resistance (Rs) < 500 Ω/□. You are using boron (B⁺) implant at 500eV, dose 2×10¹⁴ cm⁻², tilt 7°, twist 22°. SIMS profiles of the implanted wafers show three problems: (1) the boron profile has a non-Gaussian tail extending to 28nm depth — far beyond the 8nm Xj target; (2) after the post-implant anneal (850°C spike anneal, 1 second), SIMS shows the boron profile has shifted 4nm deeper and broadened significantly; (3) Rs measurements are 780 Ω/□ — 56% above the 500 Ω/□ target despite the dose being correct.

Explain the physical mechanism behind each problem and propose the implant and anneal process changes that would close all three to specification.

Why Interviewers Ask This Question

Ion implantation is the primary method for introducing dopants into silicon, and shallow junction formation for source/drain extensions at advanced nodes is one of the most technically constrained processes in semiconductor manufacturing. The three problems — channelling-induced deep tails, transient-enhanced diffusion (TED) during anneal, and incomplete dopant activation — represent the three dominant mechanisms that prevent achieving simultaneously shallow, heavily doped, low-resistance junctions. This question tests whether a candidate understands the physics of ion-crystal interactions, damage-mediated diffusion, and dopant activation kinetics at the level required to engineer solutions.

Example Strong Answer

Problem 1: Boron channelling tail extending to 28nm (target: 8nm Xj)

Physical mechanism — ion channelling in crystalline silicon:

When a boron ion enters a crystalline silicon lattice along a low-index crystallographic direction (e.g., <110> or <100> channels), it travels between rows of Si atoms with minimal nuclear collisions — experiencing only weak electronic stopping. This allows ions to penetrate to much greater depths (channelling tail) than predicted by the LSS (Lindhard-Scharff-Schiott) stopping theory, which assumes a random amorphous target.

At 500eV boron implant energy into <100> Si, the projected range (Rp) in an amorphous target would be ~4nm — well within the 8nm target. The channelling tail to 28nm indicates that a significant fraction of boron ions are entering the crystal along the <110> channel direction despite the 7° tilt.

The 7° tilt is intended to direct ions away from the primary <100> channelling direction. However, <100> silicon has many equivalent channelling directions at various tilt/twist combinations. At 7° tilt / 22° twist, ions may still be aligned with a secondary channelling axis, allowing partial channelling.

Process fixes:

• Increase tilt angle to 15–20°: A larger tilt angle (15°) provides more robust misalignment from all principal crystal axes in <100> silicon, suppressing channelling more effectively. Verify by simulating the ion trajectory at the new tilt/twist combination using SRIM/TRIM Monte Carlo code to confirm no residual channelling path alignment.

• Pre-amorphisation implant (PAI) with Ge⁺ or Si⁺: Implant germanium (Ge⁺, 30–60keV, dose 1×10¹⁴ cm⁻²) before the boron implant to amorphise the top 10–15nm of silicon. Amorphous silicon has no crystal periodicity, eliminating channelling. The boron implant into the amorphous layer follows the LSS stopping distribution — a Gaussian profile with Rp ~4nm and no channelling tail. After annealing, the amorphised Si recrystallises via solid-phase epitaxy (SPE) from the underlying crystalline Si, incorporating the boron substitutionally.

• Molecular boron implant (B₁₈H₂₂ or similar cluster ions): Use cluster ion implantation — large boron-containing molecules. At the same boron energy per atom (500eV/B), the molecular ion has much higher total energy and mass, causing immediate self-amorphisation of the Si surface on impact. The dense damage cascade from the cluster ion eliminates channelling within the first few nanometres of the impact.

Problem 2: Boron profile shifts 4nm deeper and broadens during 850°C spike anneal (1 second) — TED

Physical mechanism — Transient Enhanced Diffusion (TED):

Ion implantation creates lattice damage: Si interstitials and vacancies displaced from their lattice sites. After implantation, the silicon lattice contains far more self-interstitials than vacancies (an excess interstitial population, because the implanted ions displace Si atoms but occupy substitutional sites — storing one Si interstitial for every dopant atom at concentrations above solid solubility). This is the "+1 model" for interstitial supersaturation.

During the post-implant anneal, the excess Si interstitials are mobile at temperatures > 700°C. They form {311} rod-like defects (extended interstitial clusters) that slowly dissolve during anneal, releasing free interstitials. These free interstitials interact with substitutional boron via a kick-out mechanism: a moving Si interstitial kicks a B atom from its substitutional site to an interstitial position, allowing it to migrate rapidly (interstitial diffusion coefficient is 1,000× higher than substitutional diffusion coefficient). This transient enhancement of boron diffusion — TED — causes the profile to move deeper and broaden during the anneal far beyond what equilibrium diffusion predicts.

At 850°C for 1 second, even a spike anneal can drive TED-induced boron movement of 4nm in heavily damaged silicon.

Process fixes:

• Pre-amorphisation + solid-phase epitaxy (PAI+SPE): The PAI approach described for Problem 1 also suppresses TED. In amorphised Si, the recrystallisation front moves upward at ~10nm/second at 600°C, sweeping up excess interstitials into the growing crystal. The {311} defects that drive TED cannot form because the interstitials are consumed by SPE. This is the most effective single change for both channelling and TED suppression.

• Reduce anneal temperature + increase anneal time (flash anneal / laser spike anneal): A 1,050°C laser spike anneal (LSA) lasting only 0.5ms (vs 850°C for 1 second) provides higher peak temperature for dopant activation while drastically reducing the thermal budget available for diffusion. The high activation energy for TED means it is much slower at the start of the anneal transient — the ultrashort LSA can activate boron before TED has time to operate. The ratio of activation time to TED onset time is more favourable at higher temperature despite the higher temperature.

• Carbon co-implant for interstitial trapping: Co-implant carbon (C⁺, 5keV, dose 1×10¹⁴ cm⁻²) before or after the boron implant. Carbon atoms in silicon have a strong affinity for Si interstitials — they form C-Si interstitial complexes that are immobile at anneal temperatures and act as interstitial sinks, consuming the excess interstitials that would otherwise drive TED. Carbon co-implant can reduce boron diffusion by 50–70% with minimal impact on electrical activation.

Problem 3: Rs = 780 Ω/□ (target: 500 Ω/□) — incomplete dopant activation

Physical mechanism — substitutional incorporation and defect trapping:

Sheet resistance Rs = ρ/Xj = 1/(q × µ × Na_active × Xj). For Rs to be high despite the correct total dose, either: (a) not all implanted boron is electrically active (substitutionally incorporated on Si sites and ionised), or (b) carrier mobility µ is reduced by implant damage scattering.

At doses of 2×10¹⁴ cm⁻², the implanted boron concentration in the 8nm junction (2×10²⁰ cm⁻³) approaches or exceeds the solid solubility limit of boron in Si at the anneal temperature. Boron atoms above the solid solubility limit precipitate as inactive B₃Si or boron clusters that are not electrically active. Additionally, if the post-implant anneal does not fully remove implant damage (residual amorphous regions, end-of-range dislocation loops), boron atoms at damage sites remain trapped in non-substitutional positions and do not contribute carriers.

Process fixes:

• Increase anneal temperature for higher activation fraction: The boron solid solubility in Si increases with temperature. At 1,050°C laser spike anneal, the solid solubility is ~2×10²¹ cm⁻³ — above the target peak concentration of 2×10²⁰ cm⁻³. All implanted boron can be in solution and active. At 850°C, solid solubility is ~1×10²⁰ cm⁻³ — below the target concentration — so even after full anneal, some boron is inactive. Switch to laser spike anneal or flash lamp anneal (FLA) at 1,000–1,100°C, 0.5–2ms.

• Germanium pre-amorphisation for SPE activation: The PAI+SPE approach provides a unique mechanism for exceeding the equilibrium solid solubility — during SPE recrystallisation, boron is incorporated substitutionally faster than it can cluster, achieving "non-equilibrium" concentrations above the equilibrium solid solubility. This can achieve active boron concentrations of 3–5×10²⁰ cm⁻³ — well above the 850°C equilibrium limit.

Integrated solution — all three problems:

The optimal process change that addresses all three issues simultaneously:

1. Ge⁺ PAI (60keV, 1×10¹⁴ cm⁻²) → amorphises top 12nm, eliminating channelling

1. B⁺ implant at 500eV into amorphous Si → Gaussian profile, no channelling tail

1. C⁺ co-implant (5keV, 5×10¹³ cm⁻²) → captures excess interstitials, suppresses TED

1. Laser spike anneal at 1,050°C, 1ms → SPE recrystallisation during ramp-up, full boron activation above solid solubility, minimal diffusion

Key Concepts Tested

• Ion channelling in crystalline Si: mechanism, tilt/twist geometry, and PAI suppression

• +1 model for excess interstitial supersaturation after implant

• Transient Enhanced Diffusion (TED): {311} defect dissolution, kick-out mechanism

• Carbon co-implant as interstitial sink for TED suppression

• Boron solid solubility limit and its role in limiting electrical activation at 850°C

• SPE (Solid-Phase Epitaxy) as a non-equilibrium activation mechanism

• Laser spike anneal vs spike RTA: thermal budget and activation fraction trade-offs

Follow-Up Questions

1. "You implement Ge PAI + C co-implant + laser spike anneal. SIMS confirms the boron profile is now contained within 8nm with no channelling tail, and the profile does not shift after anneal. However, Hall effect measurements show the active carrier concentration is 1.5×10²⁰ cm⁻³ — still 25% below the SIMS total boron concentration of 2×10²⁰ cm⁻³. What is the most likely reason for the 25% activation deficit despite the LSA at 1,050°C, and what characterisation technique would you use to identify the location and chemical state of the inactive boron?"

1. "Your process uses a p-type FinFET geometry with fins oriented along <110> on a (100) substrate. The source/drain extension implant is applied simultaneously to the fin top and sidewalls. At 7° tilt, the implant hits the fin sidewall at a very different effective angle than the fin top — the fin sidewall is nearly parallel to the beam direction. Explain how this geometric effect changes the implanted depth profile on the fin sidewall vs fin top, and what implant strategy (rotation, multiple tilt angles, or plasma doping) would achieve a uniform junction depth on both surfaces."

Question 5: Yield Engineering — Statistical Process Control and Defect Root Cause Analysis

Interview Question

You are the yield engineering lead for a 3nm node logic process at a high-volume manufacturing fab. The product is an Intel-equivalent high-performance CPU die (die area 450mm²). Current yield is 52% — significantly below the 75% ramp target at this production volume. Wafer-level defect inspection data shows: total defect density D₀ = 0.18 defects/cm² on critical layers; killer defect density is estimated at 0.06 defects/cm² using a defect-to-yield correlation model. Your team's analysis of the defect map database (2,400 wafers, 6 months of production data) has identified three systematic defect sources: (1) a repeating defect pattern at the same (x, y) die location on every wafer from one specific etch chamber (Chamber 7), accounting for 22% of killer defects; (2) a random particle defect cluster that shows a strong correlation (r² = 0.78) with lot processing sequence — lots processed immediately after a preventive maintenance cycle show 3× higher defect density than baseline; (3) a subtle CD (critical dimension) drift: metal-3 line CD has been drifting +0.4nm/week for 11 weeks, is currently at nominal +4.4nm, and the process control chart shows the CD is approaching the +6nm Upper Control Limit.

For each yield loss source, describe the root cause investigation methodology, the corrective action, and how you would implement statistical process control to prevent recurrence.

Why Interviewers Ask This Question

Yield engineering is where semiconductor process knowledge, statistical methodology, and cross-functional engineering coordination converge into business impact. At advanced nodes, a 1% yield improvement on a 450mm² die at high volume can be worth tens of millions of dollars per year. This question tests whether a candidate can apply the full toolkit of yield engineering — defect density models, defect map analysis, SPC charting, root cause analysis, and corrective action workflows — to realistic manufacturing scenarios. The three defect sources represent systematic vs random vs drift failure modes, each requiring a different analytical and corrective approach.

Example Strong Answer

Yield model baseline:

Using the negative binomial yield model (appropriate for clustered defects):

Y = (1 + D₀ × A / α)^(-α)

Where:
  D₀ = 0.06 killer defects/cm² (killer defect density)
  A  = 4.5 cm² (450mm² die area)
  α  = clustering parameter (typically 2–5 for logic; use α = 3)

Y = (1 + 0.06 × 4.5 / 3)^(-3)
  = (1 + 0.09)^(-3)
  = (1.09)^(-3)
  = 0.77 → 77% yield (close to target)

Current yield is 52%, implying the effective killer defect density is higher than estimated,
or the model clustering parameter is incorrect. This discrepancy is the first investigation target.

Yield Loss Source 1: Chamber 7 repeating defect pattern — systematic tool-level defect

Root cause investigation:

A repeating defect at the same die (x, y) location on every wafer from Chamber 7 is a systematic defect — it has a deterministic, reproducible source rather than a random particle. The pattern's fixed (x, y) position maps to a fixed location on the etch chamber hardware.

Investigation steps:

1. Chamber hardware inspection: Map the defect (x, y) location on the die to the corresponding location on the etch chamber's electrode assembly, edge ring, or injector manifold. Defects at a fixed die location typically originate from: a crack in the chamber's focus ring or electrode depositing particles at a fixed plasma sheath location, an injector orifice partially blocked producing a non-uniform gas distribution, or a loose hardware component vibrating in a fixed location.

1. Chamber 7 vs healthy chamber comparison: Run a qualification wafer set on Chamber 7 and on Chamber 8 (healthy baseline). Inspect with SEM. The defect morphology (particle, etch pit, deposition nodule) will identify the failure mechanism.

1. Time-to-detect via defect frequency: Check if the defect has always been present on Chamber 7 or appeared after a specific maintenance event or process recipe change. Review Chamber 7's maintenance log and process recipe revision history for the onset date.

Corrective action:

• Immediate: Move all lots off Chamber 7 to prevent further yield loss accumulation. Chamber 7 produces 22% of killer defects — isolating it will improve yield by eliminating this source.

• Root cause fix: Disassemble Chamber 7, inspect the hardware at the mapped location, and replace the defective component. Re-qualify Chamber 7 with a full defect qualification wafer set (21-point defect map per wafer, 5 wafers) before returning to production.

SPC implementation:

• Establish a chamber-to-chamber matching SPC chart monitoring defect density per chamber per layer per day. Set a rule: if any chamber's defect density exceeds 1.5× the fleet average for 3 consecutive wafers, auto-flag for engineering review. This detects systematic tool degradation before it accumulates to a yield excursion.

Yield Loss Source 2: Post-PM defect cluster (3× higher density after maintenance)

Root cause investigation:

A 3× defect density increase immediately after preventive maintenance (PM) is a classic PM-induced contamination signature. During PM, the chamber is opened to atmosphere, components are cleaned or replaced, and residual particles from handling, cleaning chemistries, or new component outgassing are introduced.

Investigation steps:

1. Post-PM qualification wafer analysis: Run 3 qualification wafers immediately after the next PM cycle (before any product wafers) and inspect for defects. This establishes the baseline post-PM defect density and wafer position within the lot at which defect density normalises.

1. PM step-by-step isolation: On the next PM cycle, perform the PM in segments (clean only, then component replacement, then reassembly) and run a qualification wafer after each segment. The step where defect density spikes identifies the contamination source within the PM procedure.

1. Particle source identification: If the defects are metallic particles, XRF or EDX on the SEM will identify the metal species — correlating to specific PM components (e.g., stainless steel cleaning tools, aluminium components, or O-ring material).

Corrective action:

• Improve PM cleanliness protocol: Implement a cleanroom-grade PM protocol: all PM tools cleaned and certified particle-free before use, replacement components baked out to remove outgassing species, final chamber wipe with IPA-wetted cleanroom wipe after PM before pump-down.

• Extended post-PM qualification: After every PM, run 5 qualification wafers before the first product lot. Do not release for production until defect density on the 5th qualification wafer is within 10% of the fleet baseline.

• PM interval optimisation: If defect density also increases before PM (the reason PM was scheduled), the PM interval may be suboptimal — too frequent PM creates more contamination events than it prevents. Use SPC data on pre-PM defect trend to identify the optimal PM frequency.

SPC implementation:

• Track defect density as a function of wafer count since last PM for each chamber. Build a PM trigger model — if defect density rises > 20% above baseline, trigger an unscheduled inspection and potentially an early PM. This transitions from time-based PM to condition-based PM.

Yield Loss Source 3: Metal-3 CD drift +0.4nm/week, currently at +4.4nm

Root cause investigation:

A monotonic CD drift of +0.4nm/week over 11 weeks is a slow process drift — not a sudden excursion. At this rate, the CD will reach the +6nm UCL in 4 weeks. Common causes of monotonic CD drift in metal CMP and lithography:

1. Lithography OPC model drift: The optical proximity correction (OPC) model used to compute the reticle correction was calibrated to a specific process state. If the process has drifted (resist sensitivity, developer concentration, focus offset), the OPC model produces increasingly incorrect corrections, causing monotonic CD drift.

1. Etch chamber deposition accumulation: Over time, polymer and etch byproducts accumulate on the etch chamber walls, changing the local gas-phase chemistry and gradually shifting the etch CD bias in one direction. This is a classic etch drift mechanism.

1. Reticle degradation: Slow haze formation on the reticle or pellicle degradation can reduce the effective aerial image contrast, causing CD to drift. EUV reticles are particularly susceptible to hydrocarbon contamination.

Corrective action (immediate — before UCL breach):

• Manual APC (Advanced Process Control) offset correction: Apply a −4.4nm CD offset to the lithography scanner setpoint (exposure dose) or etch chemistry to return the CD to nominal immediately. This is a correction to the recipe, not a root cause fix, but it prevents a UCL breach and potential yield excursion in the next 4 weeks.

• Root cause investigation in parallel: While the offset correction holds the CD at nominal, run the etch chamber full clean (PM), measure CD before and after, and inspect the reticle for haze or contamination under the fab's reticle inspection tool.

SPC implementation:

• The current SPC chart caught this drift before the UCL breach — the SPC system is working. However, the +0.4nm/week drift over 11 weeks should have triggered a Western Electric Rule violation (e.g., 7+ consecutive points above the centreline) much earlier. Review and implement sensitivity rules: 7 points in a row above centreline → engineering alert, regardless of UCL breach.

• Implement APC (Advanced Process Control) run-to-run control for the M3 etch process. APC automatically adjusts the etch time or chemistry based on the measured CD from the previous wafer, keeping CD tightly controlled around nominal without requiring manual intervention for slow drift.

Yield recovery projection:

Key Concepts Tested

• Negative binomial yield model: killer defect density, die area, clustering parameter

• Systematic vs random vs drift defect classification: different analytical approaches for each

• Chamber-to-chamber matching SPC: fleet-level defect monitoring for tool health

• Post-PM contamination: qualification wafer protocol, step-by-step PM isolation

• Condition-based PM: SPC-triggered PM vs fixed-interval PM

• APC (run-to-run control) for CD drift correction without manual intervention

• Western Electric SPC violation rules for early detection of systematic drift

Follow-Up Questions

1. "After implementing all three corrective actions, yield improves from 52% to 71% — close to the 75% target but still 4% short. Your defect density data shows D₀ is now 0.04 killers/cm², which the negative binomial model predicts should give 79% yield — but actual yield is only 71%. This 8% gap between model-predicted and actual yield is called 'parametric yield loss' — yield loss not explained by physical defects. Name three mechanisms that cause parametric yield loss in a 3nm logic process, and explain how you would identify which is dominant."

1. "Your fab is ramping a new customer product on the same 3nm process — a mobile SoC with a much smaller die area of 80mm² (vs 450mm² for the CPU). Using the negative binomial yield model with D₀ = 0.04 killers/cm² and α = 3, calculate the predicted yield for the 80mm² die. The customer's contract requires 90% yield for the mobile SoC. Based on your calculation, explain whether this target is achievable with the current process state, and what actions you would take if the predicted yield falls short of 90%."

Question 6: Gate-All-Around (GAA) Nanosheet Transistor Fabrication and Integration

Interview Question

You are on the process integration team developing a Gate-All-Around (GAA) nanosheet transistor for a 2nm-equivalent logic node. The device stack consists of 3 silicon nanosheets (each 5nm thick, separated by 10nm sacrificial SiGe release layers, total stack height 65nm) with a target gate length of 12nm. After completing the nanosheet release etch (selective removal of the SiGe sacrificial layers to expose the Si nanosheets for gate-all-around wrapping), your characterisation reveals three integration problems: (1) after the SiGe release etch using HCl vapour at 700°C, TEM cross-sections show the bottom Si nanosheet is thinned by 1.8nm on its lower surface — a 36% thickness loss from the 5nm target; (2) during the subsequent high-k/metal gate (HKMG) fill into the 10nm inter-nanosheet gaps, C-V measurements show incomplete gate wrap-around — the gate dielectric is 1.9nm thick on the nanosheet top/sides but only 0.8nm thick in the inner nanosheet corner at the sheet-to-sheet gap minimum; (3) after the full gate module is complete and source/drain epitaxy is grown, the nSFET (n-type nanosheet FET) threshold voltage (Vth) is 85mV higher than the pSFET Vth target, and Vth distribution across 300mm wafer shows ±22mV 3σ variation.

For each problem, explain the physical and chemical mechanism causing it, and propose the process change that closes the gap to specification.

Why Interviewers Ask This Question

GAA nanosheet transistors are the successor to FinFET architecture beginning at the 2nm node — Intel's RibbonFET (Intel 20A/18A), Samsung 3GAE/2GAP, and TSMC N2 all use this structure. The three problems described are precisely the integration challenges that separate successful GAA process development from failed qualification: Si nanosheet thinning during SiGe selective etch, HKMG conformality in ultra-narrow inter-sheet gaps, and Vth control across the wafer for the dual-workfunction gate stack. This question tests whether a candidate has moved beyond FinFET process knowledge into the new physical and chemical constraints of GAA fabrication.

Example Strong Answer

Problem 1: Bottom nanosheet thinning 1.8nm during SiGe HCl release etch

Physical mechanism — geometric etch shadowing and loading in the nanosheet stack:

The HCl vapour selective etch removes SiGe sacrificial layers by exploiting the higher reactivity of Ge with HCl relative to Si. The ideal selectivity of SiGe:Si under HCl vapour at 700°C is approximately 100:1 for Si₀.₃Ge₀.₇ composition. However, the selectivity is not infinite, and the etch proceeds geometrically from the exposed SiGe edges inward as the etch front advances through the 65nm-tall nanosheet stack.

The bottom nanosheet suffers preferential thinning for two reasons:

1. Etch byproduct accumulation: HCl etching of SiGe produces GeCl₂ and SiCl₂ volatile byproducts. In a vertical nanosheet stack, these byproducts must escape upward from the bottom sheet gap — passing through the partially etched upper gaps. The bottom gap receives a higher effective HCl partial pressure from backstreaming of un-reacted HCl that has passed through the upper gaps, creating a local etch rate enhancement at the bottom sheet.

1. Temperature gradient: The bottom of the nanosheet stack, sitting on the STI oxide and fin substrate, has a slightly different thermal environment than the top sheets. If the substrate acts as a heat sink, the bottom sheet may be at a slightly lower temperature — shifting the etch selectivity because SiGe:Si HCl selectivity decreases at lower temperatures (the Si etch rate increases faster than the SiGe rate as temperature drops, reducing the selectivity ratio).

Process fix:

• Reduce etch temperature to improve Si selectivity: At 600°C instead of 700°C, the HCl etching of SiGe is slower but the Si etch rate drops more steeply (higher activation energy for Si etching by HCl than for SiGe). This improves the effective SiGe:Si selectivity at the cost of longer etch time. Run a temperature sweep (600°C, 625°C, 650°C, 700°C) and measure both etch rate and Si nanosheet thinning at each temperature to find the optimal point.

• Increase Ge content in the SiGe sacrificial layer: Moving from Si₀.₃Ge₀.₇ to Si₀.₂Ge₀.₈ improves SiGe:Si HCl etch selectivity from ~100:1 to >500:1, dramatically reducing the unintentional Si etch rate. The constraint is that higher Ge content increases lattice strain and may cause misfit dislocations during the SiGe epitaxial growth step — verify with XRD that the SiGe epitaxy remains pseudomorphic at 80% Ge.

• Cyclic etch-passivation approach: Implement a pulsed etch process: HCl exposure (2 seconds) followed by a short Si surface passivation exposure (dilute HF-last treatment or H₂ anneal, 1 second) that terminates Si surface dangling bonds and reduces the Si etch rate on subsequent HCl pulses. This cyclic approach provides more controlled selectivity, particularly at the bottom sheet where byproduct loading is highest.

Problem 2: Incomplete HKMG gate wrap — 0.8nm dielectric in inner nanosheet corners

Physical mechanism — ALD conformality limitation in ultra-narrow inter-sheet gaps:

The 10nm inter-nanosheet gap with a 12nm gate length creates an aspect ratio of 10nm/12nm ≈ 0.8:1 in the lateral direction, but the critical dimension for ALD penetration is the gap opening at the nanosheet corner — which after the SiGe release and gate spacer formation may be as narrow as 3–4nm. For a target 1.9nm HfO₂ gate dielectric, the gap must be penetrated by ALD precursor molecules to the most remote corner (the inner corner where two nanosheet surfaces and the spacer wall converge at a 3-way junction).

As explained in Question 2 (ALD conformality), the sticking coefficient of HfCl₄ in narrow gaps creates a precursor depletion gradient — the inner nanosheet corner receives less precursor per ALD cycle than exposed surfaces. In a 3–4nm-wide inner gap, Knudsen transport still applies but the geometric "shadow" at the three-way junction creates an extreme conformality challenge: the effective local ALD exposure at the inner corner may be only 40–50% of the exposed surface exposure, explaining the 0.8nm vs 1.9nm thickness ratio (0.8/1.9 ≈ 42%).

Process fix:

• Switch to a lower sticking coefficient ALD precursor — TDMAHf (tetrakis-dimethylaminohafnium) instead of HfCl₄: TDMAHf has a lower sticking coefficient on oxide surfaces than HfCl₄, allowing precursor molecules to bounce multiple times within the nanosheet gap before adsorbing — improving the probability of reaching the inner corner. The trade-off is that TDMAHf has a narrower ALD temperature window (200–250°C vs 300–400°C for HfCl₄) and may leave higher carbon impurity content in the film.

• Increase ALD exposure time and reduce deposition temperature: At lower temperature (200°C), the TDMAHf sticking coefficient decreases further and the precursor molecule has more thermal energy to diffuse through the constrained gap geometry. Extend the precursor exposure time from 0.1s to 2s per ALD half-cycle to ensure full saturation at the inner corners. Validate conformality with cross-section TEM on test structures with 3nm inner gap dimensions.

• Atomic layer etch (ALE) smoothing before HKMG: Before the HKMG deposition, apply a brief ALE (Atomic Layer Etch) step using Cl₂ adsorption + Ar⁺ ion bombardment to clean and slightly round the nanosheet inner corners. Sharp 90° corners (two flat surfaces meeting at a right angle) are inherently harder to coat conformally than rounded corners (r > 1nm). A 1–2 ALE cycle treatment that removes 0.3–0.5nm of Si from the inner corners converts the 90° geometry to a rounded profile, improving the ALD effective area at the critical junction.

Problem 3: nSFET Vth 85mV high, ±22mV 3σ wafer variation

Physical mechanism — workfunction metal fill uniformity in the inter-nanosheet gap:

GAA transistors require a metal gate fill that must wrap around all surfaces of each nanosheet. The Vth is set by the workfunction of the gate metal:

Vth = φms - Qf/Cox - 2φF + (QB/Cox)

Where φms = metal-semiconductor workfunction difference

For an nSFET, a low-workfunction metal (TiN, ~4.1–4.2 eV) is required. However, in the narrow inter-nanosheet gaps, the metal fill process (CVD or ALD of TiN) deposits the gate metal on all nanosheet surfaces. If the metal fill is not complete or the metal layer thickness varies in the gap, the effective workfunction differs from the bulk metal value — specifically:

1. Incomplete metal fill — void formation in the inter-sheet gap: If the 10nm gap is not fully filled with gate metal, a void exists at the gap centre. The silicon nanosheet in a void region sees a different dielectric boundary condition (the void has k≈1 vs metal-filled k→∞) — locally raising the Vth by 50–100mV.

1. TiN grain texture variation across the wafer: TiN workfunction depends on its crystallographic texture: (200)-textured TiN has φ ≈ 4.6eV while (111)-textured TiN has φ ≈ 4.2eV. If the TiN deposition process produces non-uniform texture across the 300mm wafer (common in PVD processes where the deposition rate varies centre-to-edge), the Vth varies systematically across the wafer.

Process fix:

• Switch gate metal fill from PVD to CVD or ALD TiN for the inner wrap layer: PVD (physical vapour deposition) has poor conformality in the inter-nanosheet gaps — the physical line-of-sight deposition cannot reach the inner gap surfaces. Replace with ALD TiN (using TiCl₄ + NH₃ at 400°C) for the first 2–3nm of gate metal, ensuring complete conformal coverage of all nanosheet surfaces including inner gaps. The bulk of the gate fill can then use a CVD WF₆ tungsten or CVD TaN process to fill the remaining void.

• Post-metal anneal for TiN texture homogenisation: A rapid thermal anneal (RTA) at 400–450°C in N₂ after TiN deposition promotes grain growth and texture homogenisation across the wafer. A uniform (200) or (111) texture across the 300mm wafer reduces the centre-to-edge Vth variation from ±22mV toward ±8mV.

• Workfunction tuning via La₂O₃ or MgO dipole layer for nSFET: Add a thin (0.3–0.5nm) lanthanum oxide (La₂O₃) dipole layer between the HfO₂ gate dielectric and the TiN gate metal for the nSFET. La₂O₃ at the high-k/metal interface creates a dipole that shifts the effective workfunction toward lower values (more n-type), allowing the TiN to achieve the target nSFET Vth even with its natural workfunction. The Vth shift from La₂O₃ is well-controlled (ΔVth ≈ −100 to −150mV per monolayer of La₂O₃) and is widely used in industry to hit dual-workfunction targets.

Key Concepts Tested

• GAA nanosheet stack structure: Si nanosheets / SiGe sacrificial layers / aspect ratios

• SiGe HCl selective etch mechanism: selectivity dependence on Ge content and temperature

• ALD conformality in sub-5nm inter-nanosheet gaps: sticking coefficient, Knudsen transport

• TDMAHf vs HfCl₄ precursor trade-offs for conformal HKMG in constrained geometry

• TiN workfunction dependence on grain texture: (200) vs (111) orientation

• Dipole layer workfunction engineering: La₂O₃ for nSFET Vth tuning

• Void formation in metal gate fill and its impact on local Vth

Follow-Up Questions

1. "After implementing ALD TiN for the inner wrap layer and La₂O₃ dipole for the nSFET, Vth uniformity improves to ±9mV 3σ. However, reliability testing (PBTI — Positive Bias Temperature Instability) shows that the nSFET Vth shifts +28mV after 1,000 seconds at 125°C, 1.0V gate stress — exceeding the 15mV reliability spec. Explain the physical mechanism of PBTI in HfO₂-based high-k gate stacks, and identify which process change you made (La₂O₃ dipole, ALD TiN, or the inner gap conformality fix) is most likely responsible for the increased PBTI, and why."

1. "The GAA process requires source/drain epitaxy grown in the nanosheet regions after gate patterning and spacer formation. For the pSFET, SiGe:B (boron-doped silicon germanium) is grown as the source/drain for compressive strain. However, you observe that the SiGe:B epi grown adjacent to the bottom nanosheet has a faceted morphology with {111} facets exposing the nanosheet sidewall, while the epi adjacent to the top nanosheet has the desired box-shaped profile. Explain the geometric and surface energy mechanism causing the faceting at the bottom nanosheet, and what process change would produce uniform box-shaped epi profiles at all nanosheet positions."

Question 7: Plasma Etch — Selectivity, Profile Control, and Aspect-Ratio-Dependent Etching

Interview Question

You are developing the tungsten contact etch process for a 3nm node logic device. The etch must open 10nm diameter contact holes through 80nm of SiO₂ ILD (interlayer dielectric), stopping on the TiN contact barrier layer beneath — an aspect ratio of 8:1. Your etch uses a fluorocarbon plasma (C₄F₈/O₂/Ar at 60mTorr, 1,500W ICP source power, −200V DC bias). Process characterisation on 100 wafers reveals three problems: (1) the contact holes at the centre of a 100µm × 100µm dense contact array have 15% smaller CD (critical dimension) than contacts at the array edge — an aspect-ratio-dependent etch (ARDE) variation; (2) the contact sidewall angle is 84° (specification: 89° ± 1°) — the contacts are too tapered, reducing the available contact area at the TiN interface; (3) TiN selectivity (SiO₂:TiN etch rate ratio) is only 8:1 — causing 9nm of TiN overetch in dense arrays where the etch time must accommodate the ARDE-slowed centre contacts.

Explain the physical mechanism driving each problem and describe the process changes that would resolve all three.

Why Interviewers Ask This Question

High-aspect-ratio contact etch is a gating process step where etch physics — ion transport, radical transport, charge accumulation, and fluorocarbon film chemistry — all interact in ways that are specific to the geometry being etched. ARDE, sidewall angle, and etch selectivity are the three parameters that etch process engineers must simultaneously optimise, and they are coupled: changes that fix ARDE often worsen sidewall angle or selectivity. This question tests deep understanding of plasma etch physics and the ability to reason about coupled parameter optimisation under real geometric constraints.

Example Strong Answer

Plasma etch physics background:

Material removal in a fluorocarbon plasma proceeds through two mechanisms operating simultaneously:

• Chemical etching: Fluorine radicals (F•) and CF_x radicals react with SiO₂ to form volatile SiF₄ and CO₂ byproducts — isotropic component

• Ion-assisted etching: Ar⁺ and CF_x⁺ ions directed by the DC bias bombard the feature bottom, enhancing the chemical etch rate directionally — anisotropic component

The sidewall profile is determined by the competition between ion-assisted etching (directional, bottom-favoured) and fluorocarbon polymer deposition (isotropic, sidewall-protective). The CF_x radicals simultaneously etch SiO₂ and deposit a thin polymer passivation film on the sidewalls that protects them from lateral etching.

Problem 1: ARDE — 15% smaller CD at centre of dense array

Physical mechanism:

ARDE in high-aspect-ratio contact etching has two primary causes:

1. Ion flux shadowing: As the contact hole deepens, ions travelling at oblique angles (off-vertical) can only reach the bottom of the hole if their trajectory fits within the cone defined by the aspect ratio. At 8:1 AR, only ions within ±7° of vertical can reach the hole bottom. In a dense contact array, adjacent contacts further restrict the effective ion solid angle — reducing the ion flux reaching the centre of deep holes relative to edge holes where the geometric shadow is asymmetric.

1. Neutral radical depletion (Knudsen transport limitation): CF_x and F radicals are neutral and travel ballistically (no ion sheath acceleration). In deep, narrow holes, neutrals entering the hole have a sticking probability on the sidewalls — the longer the hole and the denser the array, the more neutrals are consumed before reaching the bottom. Centre contacts in a dense array have reduced radical supply because neighbouring holes compete for the same flux.

Process fix:

• Increase source power (ICP power) to raise ion flux at high AR: Higher ICP power (1,500W → 2,500W) increases the ion density in the plasma, improving the ion flux available to reach deep hole bottoms. The directional ion component is less sensitive to ARDE than the neutral radical component — improving the ion-driven component of the etch helps equalize the dense vs isolated etch rates.

• Reduce operating pressure: At 60mTorr, the mean free path of neutrals is ~1mm — comparable to the contact hole depth. Reducing pressure to 20–30mTorr increases the mean free path, allowing radicals to travel deeper into the contact hole before wall collisions. Lower pressure also reduces ion scattering, improving the directionality of ion bombardment.

• Pulsed plasma operation: Implement a time-modulated plasma where the source power is pulsed (e.g., 50% duty cycle, 10kHz). During the plasma-off phase, ions and electrons are lost, but neutral radicals persist longer (longer lifetime). This creates a periodic neutral-rich phase where radicals can diffuse into deep holes without being immediately consumed by the continuously running ion-driven etch. Pulsed plasma reduces ARDE by improving the neutral-to-ion ratio at high aspect ratios.

Problem 2: Sidewall angle 84° — contacts too tapered (spec: 89° ± 1°)

Physical mechanism:

An 84° sidewall angle means the contact hole is wider at the top than at the bottom — the contacts are tapered (bowed inward as depth increases). This is caused by insufficient sidewall passivation. The fluorocarbon polymer deposited on the sidewalls during etching protects the sidewall from lateral chemical attack. If the polymer deposition rate is insufficient (too little C₄F₈, too high O₂, or too high ion bombardment removing the polymer), the sidewalls are exposed to F• and CF_x radicals and are etched laterally — widening the top of the hole more than the bottom (because the top sidewall has been exposed to the etchant for longer during the etch).

Process fix:

• Increase C₄F₈/O₂ ratio: The C₄F₈ is the polymer precursor; O₂ competes with it by oxidising the polymer on the sidewall. Increasing the C₄F₈:O₂ ratio from the current value (e.g., 4:1 → 6:1) increases the sidewall polymer deposition rate, providing better lateral passivation and producing a more vertical profile. Monitor via ellipsometry test structures to avoid over-passivation (which causes etch stop).

• Reduce DC bias voltage: The DC bias (−200V) accelerates ions toward the wafer, and ions striking the sidewall at oblique angles sputter the protective polymer film. Reducing the bias from −200V to −150V reduces the ion energy for sidewall sputtering, allowing the polymer film to build up more effectively. Trade-off: lower bias reduces the ion-assisted etch rate at the bottom, potentially slowing the etch. Compensate with slightly higher source power.

• Two-step etch: deposition-etch alternation (DEP/ETCH cycling): Implement a cyclic process alternating between a pure polymer deposition step (C₄F₈/Ar, no O₂, zero or low bias — deposits conformal polymer on all surfaces) and a pure etch step (high bias, Ar/O₂, minimal C₄F₈ — etches vertically through the polymer on the hole bottom while the sidewall polymer remains). Each cycle advances the hole depth by 3–5nm while maintaining excellent sidewall passivation. This is conceptually similar to the Bosch process used in MEMS, adapted for nanoscale contact etching.

Problem 3: SiO₂:TiN selectivity 8:1 — 9nm TiN overetch

Physical mechanism:

TiN is etched by fluorine radicals forming volatile TiF₄ — the same mechanism as SiO₂ etching by fluorine. The SiO₂:TiN selectivity depends on the relative fluorine affinity: TiN reacts with F• at a higher rate than SiO₂ at room temperature because TiN has fewer stable surface oxides protecting it (SiO₂ has a native oxide layer that is already fully oxidised and requires activation energy to etch). At the high bias and high F• concentration in the current process, TiN etches nearly as fast as SiO₂, giving the poor 8:1 selectivity.

The 9nm TiN overetch in dense areas occurs because the ARDE-slowed centre contacts require extended etch time — during this extra time, the edge contacts (already at TiN) are over-etched.

Process fix:

• Add N₂ to the etch chemistry: N₂ addition to the plasma forms a thin TiN_x surface passivation layer by reacting with Ti at the TiN surface. This nitrogen-passivated TiN surface has a higher effective etch threshold — F• must first break through the surface passivation before reacting with TiN. N₂ addition (5–10% of total gas flow) can improve SiO₂:TiN selectivity from 8:1 to 30–50:1 without significantly affecting the SiO₂ etch rate.

• Endpoint detection at TiN: Implement optical emission spectroscopy (OES) endpoint detection monitoring the TiN etch signal (Ti emission at 399nm or TiF₄ emission). When the OES signal transitions from the SiO₂-phase spectrum to the TiN-phase spectrum, immediately switch to a soft landing etch recipe with lower power and higher selectivity — this limits TiN overetch to < 2nm even with ARDE non-uniformity.

• Fix ARDE first (from Problem 1), reducing the required overetch margin: If the ARDE variation is reduced from 15% CD non-uniformity to < 3% by the pulsed plasma and pressure changes, all contacts reach TiN within a much narrower time window — the required overetch margin shrinks from 9nm to ~2nm.

Key Concepts Tested

• Ion shadowing and neutral radical depletion as the two independent ARDE mechanisms

• Knudsen transport of neutrals in high-aspect-ratio holes: sticking probability and depletion

• Fluorocarbon polymer passivation: the balance between deposition and ion-assisted removal controlling sidewall angle

• DC bias reduction and C₄F₈:O₂ ratio increase for improved sidewall passivation

• DEP/ETCH cyclic process: Bosch-adapted approach for nanoscale anisotropic etching

• N₂ addition for TiN surface passivation and improved SiO₂:TiN selectivity

• OES endpoint detection: Ti emission signal transition from SiO₂ to TiN etch phase

Follow-Up Questions

1. "After implementing pulsed plasma + reduced pressure + higher C₄F₈:O₂ ratio + N₂ addition, your contact etch now achieves ARDE < 3%, sidewall angle 88.5°, and SiO₂:TiN selectivity 35:1. However, when you characterise the TiN barrier layer after contact etch using XPS, you find that the TiN surface has a 3nm-thick TiO_xF_y compound layer — a mixture of titanium oxide and titanium fluoride — that was not present before your process changes. This surface compound layer elevates the contact resistance by 2.4× compared to the baseline process. Identify which process change most likely introduced the TiO_xF_y layer, explain the formation mechanism, and propose a post-etch clean step that removes it."

1. "A new device architecture requires etching contact holes through a new ILD material — a porous low-k dielectric (SiCOH, k = 2.4, porosity 25%) instead of the standard SiO₂ (k = 3.9). The porous low-k has 2–4nm diameter pores distributed through the bulk of the film. Explain how the porous microstructure changes the etch mechanisms for both ARDE and sidewall profile control relative to dense SiO₂, and what new process challenges arise that did not exist with dense SiO₂."

Question 8: Epitaxial Growth — Selective Epitaxy, Strain Engineering, and Defect Control

Interview Question

You are developing the source/drain epitaxial (epi) growth process for both n-type and p-type FinFETs on a 5nm node process. For the pFET, you grow SiGe:B (30% Ge, boron-doped) in the recessed source/drain regions to introduce compressive uniaxial strain in the Si channel. For the nFET, you grow Si:P (phosphorus-doped) to introduce tensile strain. After characterising 200mm test wafers, you identify three problems: (1) the SiGe:B epi shows selective growth failure — oxide residue on the SiO₂ sidewall spacers has nucleated SiGe on the spacer surfaces, creating shorts between adjacent source/drain and gate regions; (2) the Si channel of the pFET shows dislocations visible in TEM at the SiGe/Si epi interface for Ge concentrations above 28%, relaxing the intended compressive strain and degrading hole mobility by 22%; (3) the nFET Si:P epi has a phosphorus concentration of 2.5×10²⁰ cm⁻³ as grown, but after the subsequent 800°C anneal, SIMS shows the phosphorus concentration drops to 1.8×10²⁰ cm⁻³ in the first 5nm of the epi, correlated with a 35% increase in nFET contact resistance.

Diagnose the mechanism behind each problem and propose the process change that addresses it.

Why Interviewers Ask This Question

Selective epitaxial growth for source/drain stressor engineering is a critical FEOL process step that directly determines transistor drive current and contact resistance. The three problems — selectivity failure, misfit dislocation nucleation, and phosphorus segregation — are the three failure modes that process engineers encounter when pushing epitaxial stressor processes to their physical limits at advanced nodes. This question tests understanding of epitaxial growth physics, thermodynamics of strain relaxation, and dopant diffusion kinetics in the context of a real manufacturing process flow.

Example Strong Answer

Problem 1: SiGe nucleation on SiO₂ spacers — selectivity failure

Physical mechanism — oxide residue nucleation sites:

Selective epitaxial growth (SEG) of SiGe exploits the different nucleation kinetics on bare Si/Ge surfaces vs thermally grown SiO₂: SiGe readily nucleates on Si (many dangling bonds as growth sites) but nucleates very slowly on fully oxidised SiO₂ (the O-terminated surface has no Si-H surface bonds available for precursor decomposition). True selectivity requires that the SiO₂ spacer surface is fully oxidised with no Si-H dangling bonds.

The selectivity failure — SiGe growing on the spacers — indicates that the spacer SiO₂ surface has hydrocarbon or oxide residues that have created local nucleation sites. These residues arise from:

1. Incomplete pre-epi clean: The HF-last clean step (which removes native oxide from the Si surface to expose Si-H bonds for epi growth) also partially etches the SiO₂ spacer. If the HF concentration or exposure time is excessive, the SiO₂ spacer is partially etched, exposing Si-OH and Si-H sites that act as nucleation points for SiGe.

1. Organic contamination from resist strip: If the previous process step involved photoresist, residual organic compounds on the spacer surface can locally catalyse SiGe decomposition and nucleation.

Process fix:

• Optimise HF pre-clean: reduce HF concentration and time: The HF pre-clean must remove native oxide from the recessed Si source/drain surface (target: Si-H terminated) without attacking the SiO₂ spacers. Reduce HF concentration from (e.g.) 0.5% to 0.1% HF and monitor with TXRF (Total X-ray Fluorescence) to verify Si-H coverage on the Si surface while minimising spacer oxide etch. The optimal HF exposure removes ≤ 0.5nm from the SiO₂ spacers.

• In-situ H₂ bake before epi: Immediately before the SiGe growth, perform an in-situ H₂ anneal at 800°C for 60 seconds inside the epi chamber. This high-temperature H₂ bake volatilises organic residues and surface oxide species on the Si surface (forming SiH₄ that desorbs), while leaving the bulk SiO₂ spacer intact. The H₂ bake is done in-situ to prevent re-oxidation of the Si surface before growth begins.

• Cyclic deposition-etch approach for selectivity recovery: In the SiGe growth recipe, add a periodic HCl etch step (pure HCl at low partial pressure, 1 second every 10 growth cycles). HCl etches SiGe nuclei on the SiO₂ spacer surface (where the nuclei are small and weakly bonded) faster than it etches the larger epitaxial grains growing from the Si surface. This "selectivity recovery" etch removes spontaneous nuclei from the spacer continuously during growth, maintaining selectivity throughout the deposition.

Problem 2: Misfit dislocations in SiGe:B at Ge > 28% — strain relaxation

Physical mechanism — critical thickness and Matthews-Blakeslee criterion:

When SiGe is grown epitaxially on Si, the SiGe lattice must distort to match the Si substrate lattice parameter (since Si has a smaller lattice constant than SiGe: a_Si = 5.431Å, a_SiGe(30%) = 5.476Å, mismatch ε ≈ 0.83%). Below a critical thickness h_c, the SiGe film stores this mismatch elastically as biaxial compressive strain — this is the intended stressor that enhances hole mobility by splitting the heavy-hole/light-hole valence band degeneracy.

Above the critical thickness h_c (the Matthews-Blakeslee critical thickness), the elastic strain energy exceeds the energy cost of forming a misfit dislocation at the SiGe/Si interface. The film partially relieves its strain by nucleating misfit dislocations — 60° mixed dislocations that glide to the interface and create a dislocation network. Each dislocation reduces the local strain — exactly the opposite of what the stressor is designed to achieve.

For 30% Ge on Si, the Matthews-Blakeslee critical thickness is approximately 12–15nm. If the SiGe source/drain recess depth is 20nm and the SiGe fill is 20nm thick, the film exceeds h_c and dislocations nucleate. At 28% Ge (just below the failure threshold in your data), the critical thickness is slightly larger (~16–18nm) — consistent with the observed transition point.

Process fix:

• Reduce SiGe layer thickness below h_c: Design the source/drain recess depth and SiGe fill geometry so the total SiGe:B thickness in the channel strain transfer region remains below h_c for the target Ge content. For 30% Ge, this means h < 12nm of strained SiGe adjacent to the channel. Use a SiGe/Si/SiGe multi-layer stack (grade up to 30% Ge, thin strained layer, then reduce Ge) to maximise strain while staying below individual layer critical thicknesses.

• Reduce growth temperature to suppress dislocation nucleation kinetics: Misfit dislocations nucleate via thermal activation — the dislocation glide velocity has an Arrhenius dependence. Reducing the SiGe growth temperature from 650°C to 550°C reduces the dislocation glide velocity by ~100×, allowing metastable growth to a greater thickness than the thermodynamic h_c. This kinetic suppression of dislocation nucleation enables strained SiGe growth beyond the equilibrium critical thickness. The trade-off is slower growth rate and potentially higher defect density from other mechanisms at lower temperature.

• Use a SiGe:B/Si:B cap layer sequence: Grow SiGe:B to just below h_c (e.g., 10nm at 30% Ge), then cap with 5–10nm of Si:B. The Si cap provides a tensile capping stress on the SiGe that partially compensates the SiGe's compressive mismatch at the surface — reducing the total elastic energy stored and delaying dislocation nucleation. The Si cap also reduces the surface step density that seeds dislocation nucleation.

Problem 3: Phosphorus loss in first 5nm of Si:P epi after 800°C anneal — surface segregation

Physical mechanism — phosphorus surface segregation:

Phosphorus in silicon has a strong thermodynamic driving force to segregate to the free surface (or to interfaces). The surface segregation energy of P in Si is approximately −0.3 to −0.5 eV — meaning P atoms preferentially occupy surface sites over bulk substitutional sites. During the 800°C anneal, phosphorus atoms near the Si:P epi surface diffuse to the surface and form a phosphorus-enriched surface layer, depleting the subsurface region.

The surface-segregated phosphorus is electrically inactive (surface P is not in a substitutional donor configuration) and is partially lost to the gas phase or to the surface oxide (SiO₂ cap that forms during anneal). This explains:

1. The SIMS concentration drop from 2.5×10²⁰ to 1.8×10²⁰ cm⁻³ in the first 5nm (P has segregated away from this region)

1. The elevated nFET contact resistance (the top 5nm of Si:P, which is the actual metal contact interface, is now under-doped)

Process fix:

• Grow a heavily doped P cap layer immediately before anneal: Since surface segregation depletes P from the subsurface, compensate by growing an additional 3–5nm of Si:P at 2× the target concentration (5×10²⁰ cm⁻³) as a sacrificial cap. During the 800°C anneal, P segregates from this cap layer rather than from the device-active subsurface region. After anneal, etch back the cap to expose the underlying well-doped Si:P. This is the "delta-doping cap" technique used in advanced Si:P epi processes.

• Reduce anneal temperature and time: The extent of surface segregation follows an Arrhenius dependence on temperature. Reducing the anneal from 800°C to 650°C and extending the time (to maintain total thermal budget for dopant activation) reduces the P surface diffusivity by 5–10×, limiting segregation depth from 5nm to < 1nm.

• Nitrogen surface passivation before anneal: Expose the Si:P epi surface to a brief NH₃ anneal at 400°C before the 800°C step. This deposits a monolayer of Si-N at the surface that acts as a diffusion barrier, blocking P surface segregation to the free surface. The Si-N monolayer is thin enough that it does not significantly increase contact resistance when the silicide is formed subsequently.

Key Concepts Tested

• Selective epitaxy nucleation kinetics: Si vs SiO₂ surface site availability

• HF pre-clean trade-offs: Si-H activation vs spacer SiO₂ attack

• Matthews-Blakeslee critical thickness: elastic strain energy vs dislocation formation energy

• Kinetic suppression of misfit dislocations at reduced growth temperature

• Phosphorus surface segregation thermodynamics in Si:P epi

• Delta-doping cap technique for segregation compensation

• Cyclic deposition-etch (SiGe + HCl) for maintained selectivity during growth

Follow-Up Questions

1. "Your SiGe:B epi now grows selectively on Si without spacer nucleation, and the Ge profile is below the critical thickness for dislocations. You measure the channel strain by nano-beam diffraction (NBD) in TEM and confirm 0.95% compressive strain in the Si channel — close to the 1.0% target. However, after the full device is fabricated and electrical testing is complete, the pFET drive current (Id_sat) is only 85% of target despite correct strain. Identify three mechanisms other than channel strain magnitude that could reduce Id_sat in a FinFET with correct source/drain stressor, and how you would characterise each."

1. "The process integration team proposes adding a Si₀.₅Ge₀.₅ (50% Ge) stressor layer to improve pFET drive current by 30%. Using the Matthews-Blakeslee framework, estimate how the critical thickness changes going from 30% Ge to 50% Ge, and explain what process architecture changes (in the epi growth, source/drain recess geometry, or thermal budget) would be required to use 50% Ge without causing misfit dislocation nucleation."

Question 9: Diffusion, Thermal Processes, and Thermal Budget Management

Interview Question

You are the thermal process engineer for a 3nm node logic device. The process flow includes 14 sequential thermal steps after the gate stack formation, including multiple anneals for dopant activation, silicide formation, and dielectric densification. Your thermal budget model shows that the cumulative diffusion of boron from the pFET source/drain into the channel region across these 14 steps causes a 3.2nm channel length reduction (from the drawn 12nm to an effective 8.8nm), degrading the short-channel characteristics and increasing off-state leakage (Ioff) by 4× above the specification. Additionally, the thermal model predicts that the nickel silicide (NiSi) contact formation anneal at 350°C causes 2.1nm of Ni diffusion into the Si:P nFET source/drain, creating a Ni-rich silicide tail that raises the specific contact resistivity by 60%.

Explain the physical mechanisms driving each problem and design the thermal budget management strategy that preserves gate stack integrity and junction profiles while meeting all downstream process requirements.

Why Interviewers Ask This Question

Thermal budget management is one of the most cross-cutting engineering challenges in FEOL process integration — every thermal step downstream of the transistor formation affects the dopant profiles, silicide morphology, and dielectric quality established in upstream steps. This question tests whether a candidate can reason about thermal budget as a cumulative quantity (the integral of Dt, where D is the diffusivity and t is time), understand how competing requirements across 14 process steps must be balanced, and design a thermal architecture that satisfies all constraints simultaneously.

Example Strong Answer

Thermal budget physics background:

The critical thermal budget parameter for dopant diffusion is the Dt product (diffusivity × time):

Junction displacement ΔXj ≈ 2√(D(T) × t)

Where D(T) = D₀ × exp(-Ea / kT)

For boron in Si:
  D₀ = 0.76 cm²/s
  Ea = 3.46 eV
  At 900°C: D(B) ≈ 3×10⁻¹⁵ cm²/s
  At 700°C: D(B) ≈ 3×10⁻¹⁸ cm²/s  (1,000× slower)

The Arrhenius dependence means that reducing temperature by 200°C reduces diffusion rate by 1,000×. This is the fundamental lever for thermal budget reduction.

Problem 1: 3.2nm boron channel encroachment across 14 post-gate thermal steps

Root cause — cumulative Dt from sequential moderate-temperature steps:

The 14 post-gate thermal steps may individually seem low-risk, but their cumulative Dt product drives significant boron diffusion. A simple audit:

The dielectric densification steps (700°C, 30 minutes each) are the dominant thermal budget consumers — not the high-temperature anneals (which are short) and not the low-temperature steps. This is a common and counterintuitive result: a 700°C step for 30 minutes contributes more boron diffusion than an 850°C step for 1 second because the Dt product is larger despite the lower temperature.

Thermal budget management strategy:

• Replace high-temperature dielectric densification with plasma-enhanced densification (PEALD → UV cure): Conventional dielectric densification at 700°C can be replaced by UV-assisted curing or e-beam curing at 400°C. UV photons break Si-OH bonds and promote Si-O-Si network formation without requiring thermal energy — achieving equivalent dielectric density at 400°C. This converts two 700°C/30-minute steps (Dt ≈ 6×10⁻¹³ cm²) to two 400°C/30-minute steps (Dt ≈ 10⁻¹⁹ cm² — effectively zero boron diffusion).

• Consolidate anneals via spike/flash anneal sequencing: Where two separate dopant activation anneals were planned (e.g., n-well and p-well activations at different times), consolidate into a single combined anneal after all implants are complete. Each elimination of a redundant thermal step directly reduces cumulative Dt. For the remaining necessary anneals, switch from RTA (5–10 second soak) to spike anneal (< 1 second at peak temperature) to millisecond laser anneal, minimising soak time at peak temperature.

• Thermal budget allocation model: Build a full Dt budget tracker across all 14 steps. Assign each step a Dt "budget allocation" — the maximum Dt it is allowed to contribute — based on the sensitivity of the junction profile to each step. Steps that occur before junction formation have no budget constraint; steps after junction formation are tightly constrained. Use the Dt tracker to immediately flag any process change that would exceed a step's allocation.

Problem 2: Ni diffusion 2.1nm into Si:P during NiSi anneal — elevated contact resistivity

Physical mechanism — Ni diffusion in Si:P during silicidation:

NiSi formation follows a two-phase transformation:

• Phase 1 (~250°C): Ni₂Si nucleation (Ni-rich phase, high resistivity)

• Phase 2 (~350°C): Ni₂Si → NiSi transformation (stoichiometric, low resistivity target phase)

The 350°C anneal drives the Ni₂Si → NiSi transformation but simultaneously allows residual Ni to diffuse beyond the growing silicide front into the underlying Si:P. The diffusivity of Ni in Si at 350°C is approximately D_Ni ≈ 10⁻¹² cm²/s — much higher than boron diffusivity at the same temperature. In 60 seconds: √(D_Ni × t) = √(10⁻¹² × 60) ≈ 7.7nm — consistent with the observed 2.1nm average Ni tail (the full diffusion profile would show a Gaussian tail extending to ~8nm, with the SIMS-visible tail starting at ~2nm above the background detection limit).

The Ni-rich tail (NiₓSi with x > 1) has higher resistivity than stoichiometric NiSi and disrupts the phosphorus donor profile by trapping P in the silicide tail region — both effects raising the specific contact resistivity.

Process fix:

• Two-step silicidation: lower temperature Phase 1 + controlled Phase 2:
  • Phase 1: 220°C, 30 seconds → forms Ni₂Si selectively (very low Ni diffusivity at 220°C, D_Ni ≈ 10⁻¹⁴ cm²/s)
  • Selective etch: strip unreacted Ni with H₂SO₄:H₂O₂ (SPM clean) — removes Ni from dielectrics, preserving Ni₂Si on Si
  • Phase 2: 350°C, 30 seconds (reduced from 60 seconds) → converts Ni₂Si → NiSi with minimal additional Ni diffusion (source of Ni is now Ni₂Si, not metallic Ni; transformation is diffusion-controlled but with bounded Ni supply)

• Replace NiSi with NiPtSi (platinum-alloyed nickel silicide): Adding 5–10% Pt to the Ni deposition (cosputtering NiPt) incorporates Pt into the silicide. Pt in NiSi retards Ni diffusion (Pt acts as a diffusion barrier within the silicide lattice) and suppresses the NiSi → NiSi₂ phase transformation at higher temperatures (NiSi₂ is a high-resistivity phase that degrades silicide performance). NiPtSi is the industry standard silicide precisely for this stability benefit — it reduces Ni tail diffusion and improves thermal stability by 50–100°C.

• Reduce Si:P recess depth before silicidation: If the Si:P epi cap above the contact is 10nm thick and Ni diffuses 2.1nm into it, the Ni tail occupies 21% of the contact depth — a large fraction. Increase the Si:P epi cap thickness from 10nm to 20nm. This doesn't reduce the Ni diffusion depth, but reduces the fraction of the contact depth affected from 21% to 10.5%, lowering the average contact resistivity impact.

Key Concepts Tested

• Dt product as the fundamental thermal budget metric: cumulative across all steps

• Arrhenius temperature dependence: 200°C temperature reduction = 1,000× diffusivity reduction

• Dielectric densification as the dominant thermal budget consumer (long time, moderate T)

• UV/e-beam cure as zero-Dt alternative to thermal densification

• NiSi two-phase transformation: Ni₂Si at 250°C, NiSi at 350°C

• Ni diffusivity in Si at 350°C: quantitative tail depth calculation

• NiPtSi: Pt-alloying for diffusion suppression and phase stability improvement

Follow-Up Questions

1. "Your thermal budget model shows that after implementing UV cure and consolidated spike anneals, the cumulative boron Dt is reduced from 6.4×10⁻¹³ cm² to 8×10⁻¹⁴ cm². Using the diffusion displacement formula ΔXj ≈ 2√(Dt), calculate the new channel length reduction, and verify whether it meets the requirement that effective channel length remains > 11nm (drawn 12nm minus maximum 1nm encroachment). Then identify which single remaining thermal step contributes the most to the residual Dt budget."

1. "The process team proposes replacing all 14 post-gate anneals with a single end-of-line laser spike anneal (LSA) at 1,050°C/1ms that would simultaneously activate all dopants, densify all dielectrics, and form the silicide. Evaluate this proposal: what are the advantages in terms of thermal budget reduction, and what are the fundamental process integration obstacles that make this approach impractical for at least three of the 14 steps?"

Question 10: Process Integration — Stress Engineering and Mobility Enhancement

Interview Question

You are the process integration engineer responsible for mobility enhancement in a 5nm node FinFET process. Electrical measurements on finished devices show that nFET electron mobility is 87% of the unstrained silicon universal mobility curve, and pFET hole mobility is 91% of the unstrained silicon universal mobility. Both are below the targets of 115% (nFET) and 130% (pFET) of unstrained mobility — meaning the strain engineering is not delivering the expected performance gain. Process characterisation shows: (1) nFET fins have a residual compressive stress of −0.3 GPa along the channel direction, instead of the intended +0.8 GPa tensile stress from the tensile contact etch stop layer (CESL) and tensile STI fill; (2) pFET fins show only +0.4 GPa compressive channel stress from the SiGe:B source/drain stressor, versus the target +1.2 GPa; (3) XRD pole figure analysis shows the Si fins have a <110> texture along the fin length direction on the (100) substrate — the substrate miscut is 0.5° off the intended (100) orientation.

Diagnose the root cause of each stress shortfall and propose the process integration changes needed to achieve the target channel stress values.

Why Interviewers Ask This Question

Strain engineering is one of the most powerful performance levers in advanced CMOS — Intel introduced strained silicon at the 90nm node and every subsequent generation has increased the strain magnitude and diversity of stress sources. Understanding how each process module contributes to or opposes the net channel stress — and how the contributions interact — requires a system-level view of process integration that goes beyond individual process expertise. This question tests whether a candidate can reason about stress as a vector quantity, understand how multiple stress sources combine in a FinFET geometry, and diagnose why a strain target is not being met.

Example Strong Answer

Stress engineering physics background:

Channel stress in a FinFET arises from multiple superimposed contributions:

σ_channel = σ_STI + σ_CESL + σ_S/D_stressor + σ_gate + σ_substrate_miscut

For nFET (need tensile σ_channel > 0 for electron mobility):
  Target: σ_channel = +0.8 GPa tensile

For pFET (need compressive σ_channel < 0 for hole mobility):
  Target: σ_channel = −1.2 GPa compressive

Problem 1: nFET residual compressive −0.3 GPa instead of +0.8 GPa tensile

Root cause — stress cancellation from multiple compressive contributions:

The intended tensile stress in the nFET channel comes from:

• Tensile CESL: SiN deposited with tensile internal stress acts as a "stretching" film over the fin, coupling tensile stress longitudinally into the channel — target contribution: +0.6 GPa

• Tensile STI: SiO₂ STI fill has inherent tensile stress that squeezes the fin in the horizontal direction, but via Poisson's ratio, extends it longitudinally — target contribution: +0.4 GPa

However, measuring only −0.3 GPa net compressive stress means either: (a) the CESL or STI tensile contributions are absent or inverted, or (b) an unintended compressive contribution is overwhelming the tensile sources.

Investigation:

1. Measure CESL stress independently: Deposit the tensile SiN CESL on a blanket unpatterned wafer and measure the film stress via wafer bow measurement. If the CESL shows compressive stress (wafer bows convex upward) instead of tensile stress (wafer bows concave upward), the CESL deposition process has drifted — likely caused by a change in silane:NH₃ ratio, deposition temperature, or RF power that converted the film from tensile to compressive.

1. Check STI fill stress: The SiO₂ STI fill is typically deposited by HDP-CVD (High Density Plasma CVD) or SA-CVD (Sub-Atmospheric CVD). HDP-CVD SiO₂ can have either tensile or compressive stress depending on the Ar sputter-to-deposition ratio. If the Ar flow was increased in a recent recipe change, the STI fill may have shifted toward compressive.

Process fix — CESL:

• Retune the SiN CESL deposition to recover tensile stress: increase NH₃/SiH₄ ratio, increase deposition temperature, reduce RF frequency (low-frequency RF promotes compressive stress; high-frequency RF promotes tensile stress in SiN). Target CESL biaxial tensile stress of +1.5 GPa (blanket film measurement).

• Consider replacing CESL with a stress-memorisation technique (SMT): perform a selective ion implant into the nFET fins after gate formation to amorphise the Si locally, then anneal. The SPE recrystallisation of the implanted Si region introduces tensile stress that is "memorised" in the crystal structure — this stress persists through subsequent thermal steps more reliably than film stress from overlying dielectrics.

Problem 2: pFET compressive stress only +0.4 GPa instead of +1.2 GPa from SiGe:B S/D

Root cause — SiGe Ge content and volume insufficient for target stress transfer:

The compressive stress transferred to the Si channel from SiGe:B source/drain depends on:

1. The biaxial mismatch strain of SiGe on Si (proportional to Ge content: ε ≈ 0.042 × x_Ge)

1. The volume and proximity of the SiGe stressor to the channel (stress transfer efficiency)

1. The absence of dislocation-induced relaxation (as discussed in Question 8)

If the pFET is achieving only 33% of the target stress (+0.4 of +1.2 GPa), one of three causes is likely:

1. Ge content is below the 30% target: If the Si₀.₇Ge₀.₃:B epi is actually growing as Si₀.₈₅Ge₀.₁₅ due to a precursor flow calibration error, the mismatch strain is halved — directly halving the stress transfer to the channel.

1. SiGe recess geometry insufficient: If the source/drain recess depth (the depth below the channel midline where SiGe is grown) is shallower than designed, the SiGe volume adjacent to the channel is reduced, and stress transfer efficiency drops. Stress transfer scales approximately as (stressor volume / channel volume)^(2/3).

1. SiGe partial strain relaxation: As discussed in Question 8, if Ge > 28% exceeds the critical thickness, dislocations relax the SiGe — the misfit dislocations reduce the compressive mismatch strain transferred to the channel.

Process fix:

• Verify Ge content by XRD rocking curve on SiGe test wafers: Measure the SiGe lattice parameter by (004) rocking curve and calculate actual Ge content. If below 30%, recalibrate the GeH₄:SiH₄ precursor flow ratio in the epi recipe.

• Increase source/drain recess depth: Increase the recess etch depth from (e.g.) 20nm to 30nm below the fin top surface to bring the SiGe stressor closer to the channel midplane. This increases stress transfer efficiency. Validate with nano-beam diffraction (NBD) in TEM to confirm increased channel stress magnitude.

• Increase Ge content with kinetic dislocation suppression: As discussed in Q8, use reduced growth temperature (550°C) to kinetically suppress dislocation formation at higher Ge content. Push Ge to 35–40% with the kinetic suppression approach — increasing the mismatch strain by 17–33% beyond the 30% Ge target.

Problem 3: <110> fin texture on 0.5° miscut substrate — mobility anisotropy

Physical mechanism — substrate miscut and fin orientation mobility mismatch:

Silicon hole mobility is strongly anisotropic with crystal orientation:

• Holes in <110> direction on (110) plane: highest mobility (6× universal)

• Holes in <100> direction on (100) plane: lowest mobility (1× universal, reference)

Standard FinFETs are designed with fins oriented along <110> on a (100) substrate — the fin sidewalls are {110} planes, which are the highest hole mobility planes for pFET. A 0.5° substrate miscut rotates the (100) substrate slightly, creating a surface that is a vicinal cut between (100) and (110). The fin lithography, which aligns fins to the flat/notch of the wafer (nominally along <110>), may be producing fins that are actually oriented 0.5° off the ideal <110> direction due to the miscut.

The XRD pole figure confirms <110> texture along the fin length — this is correct for pFET. The issue causing mobility below target may be the combination of: (a) the miscut creating {111} facets on the fin sidewalls at the STI interface, disrupting the smooth {110} sidewall plane, or (b) the 0.5° miscut is insufficient to be the primary cause — investigate whether the low stress (Problem 2) is the dominant mobility limiter.

Process fix:

• Wafer procurement specification: tighten miscut tolerance to < 0.1°: For the next wafer lot, specify tighter miscut control (0.5° → ≤ 0.1°) from the silicon crystal grower. A 0.5° miscut introduces systematic step-edge defects on the {110} fin sidewalls that act as interface scattering sites, reducing effective mobility.

• Fin sidewall surface treatment — hydrogen anneal for step-edge smoothing: Apply a high-temperature H₂ anneal (1,000°C, 60 seconds) after STI CMP and before gate oxidation. The H₂ anneal causes Si surface atom migration that smooths the step-edge density on the fin sidewalls — converting rough vicinal surfaces into smooth terraced surfaces. This reduces surface roughness scattering of both electrons and holes, recovering 5–10% of mobility loss attributable to sidewall roughness.

Net mobility impact summary:

Implementing all three stress fixes:

• nFET: tensile CESL retune (+0.8 GPa tensile achieved) → electron mobility ~110–115% of universal ✓

• pFET: Ge content increase + deeper recess → +1.1–1.2 GPa compressive → hole mobility ~125–132% ✓

• Substrate miscut correction + H₂ fin anneal → additional 5–8% mobility recovery across both nFET and pFET

Key Concepts Tested

• Multi-source stress superposition in FinFET channels: CESL, STI, S/D stressor, gate

• SiN CESL stress dependence on NH₃/SiH₄ ratio and RF frequency

• Stress memorisation technique (SMT) as an alternative tensile stress source

• SiGe:B stress transfer efficiency: dependence on volume, proximity, and Ge content

• Silicon hole mobility anisotropy: <110>/{110} highest mobility plane

• Substrate miscut effects on fin sidewall crystallographic quality

• H₂ anneal for fin sidewall roughness reduction via surface atom migration

Follow-Up Questions

1. "After implementing the CESL retune, Ge content increase, and substrate miscut correction, nFET electron mobility reaches 113% of universal and pFET hole mobility reaches 128% of universal — both meeting or approaching the targets. However, reliability testing reveals a new failure mode: the pFET devices with 38% Ge SiGe:B source/drain show 2× higher hot carrier injection (HCI) degradation rate compared to the 30% Ge baseline. Explain the physical mechanism by which higher Ge content in the SiGe:B source/drain could increase HCI degradation in the Si channel, and propose a device design or process change that reduces HCI without sacrificing the strain benefit."

1. "The process team is evaluating whether to transition from a (100) substrate with <110>-oriented fins (current approach) to a (110) substrate with <100>-oriented fins for the next process node. Construct the argument for and against this substrate rotation from a mobility and process integration perspective, considering: hole mobility, electron mobility, etch anisotropy for fin patterning, epitaxial growth kinetics on {100} vs {110} surfaces, and the impact on existing process recipes that were qualified on (100) substrates."